This invention relates to adders, and more particularly, to configurable hybrid adders for programmable integrated circuits.
Adders are used to perform binary addition in digital integrated circuits. For example, a five bit adder may be used to compute a binary sum of two five bit binary inputs.
Adders are widely used on integrated circuits such as programmable logic devices. Programmable logic device integrated circuits contain programmable logic that may be programmed to implement a desired custom logic design. In some device architectures, programmable logic is organized in regions. Each logic region may contain configurable adder circuits. When a logic designer desires to implement an adder that is larger than an individual adder circuit, the circuitry on the programmable logic device can be selectively configured to combine multiple adder circuits.
With conventional adder architectures, the larger adders that are formed in this way may exhibit undesirably long delay times or may be insufficiently flexible to accommodate commonly desired adder widths. For example, conventional ripple carry adders may be combined by forming a carry chain. During operation, a carry signal ripples through multiple adder stages in the chain in series. This type of architecture can be used when forming adders of different desired widths on a programmable logic device, but results in delay times that scale linearly with the number of bits in the adder. Other adder architectures such as the carry look ahead adder architecture have been developed that perform addition more rapidly than ripple carry adders. However, these adder architectures are generally not as flexible as ripple carry architectures and have therefore not been used in configurable adder circuits on conventional programmable logic devices.
It would therefore be desirable to be able to provide improved adder circuitry for integrated circuits such as programmable logic device integrated circuits.